This invention relates to a transfer controlling arrangement for use in an information processing system operable as a super computer in controlling transfer requests for transfer of memory contents to and from an extended buffer memory.
In the manner known in the art, such an information processing system comprises a first and a second main memory, a peripheral device, an extended buffer memory, a central processor, an input-output processor connected to the peripheral device, an arithmetic processor, and a system controller connected to the memories and to the processors. The first main memory is for memorizing control programs and control data for the central processor. The peripheral device is for storing additional control programs and control data. The input-output processor is for producing, among others, a transfer request for transfer of a selected one of the control programs and the control data between the first main memory and the peripheral device through the system controller. The second main memory and the extended buffer memory are for storing arithmetic programs or user programs and arithmetic data for the arithmetic processor.
When issued by the central processor, a transfer request is controlled by the system controller to transfer a selected one of the control programs and the control data from the first main memory to the second main memory as a selected one of the arithmetic programs and the arithmetic data through the system controller. When issued by the central processor, another transfer request is controlled by the system controller to transfer a selected one of the arithmetic programs and the arithmetic data from the second main memory to the first main memory as a selected one of the control programs and the control data. When produced by the arithmetic processor, a transfer request is controlled by the system controller to transfer a selected one of the arithmetic programs and the arithmetic data between the second main memory and the extended buffer memory.
It has therefore been unavoidable to interrupt operation of the arithmetic processor either on transferring a selected one of the control programs and the control data from the first main memory to the extended buffer memory as a selected one of the arithmetic programs and the arithmetic data through the system controller or on transferring a selected one of the arithmetic programs and the arithmetic data from the extended buffer memory to the first main memory as a selected one of the control programs and the control data through the system controller. Interruption has also been inevitable either on transferring a selected one of the control programs and the control data from the peripheral device to the extended buffer memory as a selected one of the arithmetic programs and the arithmetic data through the input-output processor and the system controller or on transferring a selected one of the arithmetic programs and the arithmetic data from the extended buffer memory to the peripheral device as a selected one of the control programs and the control data through the system controller and the input-output processor.
Depending on the circumstances, it is possible to consider the first and the second main memories collectively as a main storage for storing arithmetic programs and data for the arithmetic processor. In this event, the peripheral stores stores additional arithmetic programs and data. The input-output processor is for producing a transfer request for transfer of a selected one of the arithmetic programs and data between the main storage and the peripheral device through the system controller. The control programs and data may alternatively be called control contents. The arithmetic programs and data may be called arithmetic contents.
The central, the input-output, and the arithmetic processors are independently operable although the input-output and the arithmetic processors are controlled by the central processor through the system controller in the manner which will be exemplified later in the following description. This gives a high speed throughput to the information processing system. Interruption of operation of the arithmetic processor, however, degrades the throughput.